Senior Photonics Engineer

Lyte builds perception systems for Physical AI operating in complex environments. The company combines custom silicon, integrated sensors, and software into a unified platform for robotics, mobility, and next-generation automation. Lyte is headquartered in Sunnyvale, California, with a global presence. For more information, visit (Use the "Apply for this Job" box below)..ai

Lyte builds perception systems for Physical AI operating in complex environments. The company combines custom silicon, integrated sensors, and software into a unified platform for robotics, mobility, and next-generation automation. Lyte is headquartered in Sunnyvale, California, with a global presence. For more information, visit  If you’re excited about building impactful technology in a dynamic, hands‑on environment, we’d love to hear from you!

• We are seeking a senior Photonics Engineer to design silicon photonic devices, subcircuits, and photonic integrated circuits (PICs) for Lyte’s next‑generation perception systems. As a member of the Photonics Design and Architecture team, you will translate architecture‑level requirements, including optical link budgets, component specifications, and interface requirements, into optimized designs, validated simulation models, and tapeout‑ready layouts. This is a hands‑on technical role with end‑to‑end ownership of assigned components and subcircuits, from simulation and layout through design verification, tapeout, and documentation.
  
  You will work closely with the silicon team, which owns test and validation, and deliver complete design handoffs that enable transfer to production.

• Design photonic components and subcircuits. Design passive and active silicon and silicon nitride devices, including couplers, splitters, interferometers, polarization‑management components, phase shifters, switches, and optical interfaces.
• Simulate and optimize performance. Use electromagnetic, optical‑circuit, and thermal simulation to predict device behavior. Optimize designs against specifications for insertion loss, bandwidth, polarization response, footprint, power, and fabrication tolerance.
• Contribute to architecture definition. Provide device‑level performance models, simulation data, and tradeoff analyses that inform optical link budgets, component specifications, interface requirements, and performance margins.
• Develop tapeout‑ready layouts. Implement component and subcircuit layouts in accordance with foundry design rules, run design‑rule checks, and prepare design files for review and integration into full PIC layouts.
• Verify designs and support tapeout signoff. Evaluate nominal performance, process sensitivity, and operating‑condition limits. Document assumptions, margins, and open risks, and present results in design reviews and cross‑functional tapeout signoff.
• Advance the PDK. Develop and maintain parameterized cells (PCells), compact models, component documentation, and reusable design elements. Update models and design guidance as characterization data become available.
• Automate engineering workflows. Build Python tools for simulation setup, parameter sweeps, optimization, layout generation, and data analysis. Maintain reproducible workflows and version‑controlled design assets.
• Co‑design for optical and system integration. Incorporate requirements for III–V sources, free‑space coupling, packaging, thermal management, and electrical interfaces into device and subcircuit designs. Work with the III–V, packaging, and IC teams to close interface requirements.
• Partner with the silicon team on test and validation. Define test structures, design‑of‑experiment (DOE) splits, and characterization objectives. Provide predicted responses and measurement priorities,…