Pre-Silicon Digital Verification Engineer: SystemVerilog​/UVM

Apple Inc. in Sunnyvale seeks a pre-silicon digital verification engineer to verify complex digital IPs for mixed-signal ICs.

You will work with system architects and digital designers to translate specifications into verification plans and block-level tests, and own the verification testbench creation, using formal verification and UVM-based simulation. You will participate in code reviews of other blocks, learn advanced techniques such as formal verification and mixed-signal simulation, and

For the Pre-Silicon Digital Verification Engineer:
System Verilog/UVM position at Apple Inc., we are reviewing applications now.

Join us at Apple Inc. as our next Pre-Silicon Digital Verification Engineer:
System Verilog/UVM in Sunnyvale, CA, United States.

We are currently recruiting a Pre-Silicon Digital Verification Engineer:
System Verilog/UVM for our team in Sunnyvale, CA, United States.

This is an excellent opening to take on the Pre-Silicon Digital Verification Engineer:
System Verilog/UVM role at Apple Inc.