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Senior ASIC Physical Design Engineer

Job in Sunnyvale, Santa Clara County, California, 94087, USA
Listing for: Anysilicon
Full Time position
Listed on 2026-10-16
Job specializations:
  • IT/Tech
    Systems Engineer, AI Engineer (Applied/Software), Hardware Engineer
Salary/Wage Range or Industry Benchmark: 180000 - 240000 USD Yearly USD 180000.00 240000.00 YEAR
Job Description & How to Apply Below

Tensordyne, a leading AI system solution company, specializes in high-performance, low-power generative AI inference systems. With a mission to accelerate multimodal generative AI inference at scale, Tensordyne is at the forefront of innovation in AI technology. The company, headquartered in Sunnyvale, CA, and Munich, Germany, offers a supportive work environment with comprehensive benefits and competitive compensation, aiming to build a healthy and motivated team to drive technological advancements.

Responsibilities:

  • Lead ASIC front-end physical design and engineering workflow development for generative AI inference products.
  • Guide and assist colleagues in improving frontend physical design at both block and full-chip levels.
  • Drive optimization, implementation, and exploration of new frontend physical design workflows, including synthesis, formal checks, and power analysis.
  • Provide guidance for static timing analysis (STA) and contribute to the full ASIC chip design process.
  • Innovate and improve scalable, reliable, high-performance systems and tools for next-generation products.
  • Collaborate closely with ASIC team members to understand and enhance their workflows and EDA needs.

Qualifications:

  • 10 years of hands‑on ASIC engineering experience with deep knowledge of VLSI/SoC chip physical design workflows.
  • Experience with EDA tools like Cadence/Synopsys (Genus/DC), power analysis, and clock methodology.
  • Strong physical design knowledge for front-end optimization using standard EDA tools.
  • Experience leading backend design teams with understanding of clock trees, routing, DRC, LVS, and metal fill until artwork release.
  • Understanding of STA analysis and constraints for block level and full chip timing analysis.
  • Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.

Skills:

  • Excellent analytical, written, and verbal interpersonal skills.
  • Ability to collaborate productively within a global engineering team in a fast‑paced startup environment.
  • Strong problem‑solving skills with a focus on designing, debugging, and optimizing EDA solutions.
Position Requirements
10+ Years work experience
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