Senior Signal & Power Integrity Lead - ASIC Packaging
Listed on 2026-10-29
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Engineering
Electronics Engineer, Packaging Engineer, Systems Engineer, Hardware Engineer
Cisco Systems is seeking a Lead Signal and Power Integrity technical leader for our Silicon One team in the US. You will head the SI/PI efforts for next-gen ASIC packaging, drive design rules for ultra-high-speed signaling, and collaborate across interposer, substrate, and PCB domains.
You will mentor engineers, drive post-layout extraction, and work with system partners to resolve complex SI/PI challenges, including 2.5D packaging considerations.
Join us at Cisco Systems as our next Senior Signal & Power Integrity Lead - ASIC Packaging in Reno, NV, United States.
We are currently recruiting a Senior Signal & Power Integrity Lead - ASIC Packaging for our team in Reno, NV, United States.
This is an excellent role to take on the Senior Signal & Power Integrity Lead - ASIC Packaging role at Cisco Systems.
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