Digital IC Design Engineer
Job in
2074, Marin-Epagnier, Neuchâtel, Switzerland
Listed on 2026-07-19
Listing for:
onsemi
Full Time
position Listed on 2026-07-19
Job specializations:
-
Engineering
Electronics Engineer, Systems Engineer, Hardware Engineer, Test Engineer
Job Description & How to Apply Below
Location: Marin-Epagnier
Staff Digital IC Design Engineer
We are looking to expand our team with a Staff Digital IC Design Engineer with experience in the development of embedded MCU/DSP systems. You will develop and benchmark such systems using various types of processor cores and consult the product integration teams during the integration of these solutions into semiconductor products. As a senior engineer you will mentor younger engineers and drive project activities.
Responsibilities- Architect, specify, implement, simulate, and benchmark MCU and DSP systems as well as hardware accelerators and peripheral IPs
- Consult the product integration teams in the definition, integration and use of these systems
- Participate in the verification and FPGA prototyping of these systems
- Coordinate the SDK development with the software team
- Lead project activities
- Contribute to design methodology and design flow improvements
- Minimum MS in Electrical Engineering or a related technical field
- At least 8 years of relevant work experience in semiconductor product development, including engineering leadership
- Experience with embedded CPUs (e.g., ARM Cortex, RISC-V, DSP), AMBA bus protocols (AHB/APB)
- RTL design of digital IP blocks and systems in Verilog/System Verilog
- Strong technical document writing skills
- Excellent written and verbal communication skills in English
- Eligibility to work in Switzerland
- Project/task leadership
- Design of CPU/MCU (sub) systems, SystemRDL or IP-XACT
- Programming in Python for automation and in C/C++ for embedded software
- Design intent (timing constraints/SDC, power intent/UPF)
- Design of accelerators and signal processing components
- RTL to GDS flow, including logic synthesis, place-and-route, STA, power analysis
- Advanced digital verification methodology (e.g., UVM)
25 vacation days per year, competitive benefits package.
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