RF SoC Design Engineer

RF SoC System Timing Design And Validation Engineer

Job Responsibilities:

Help guide chip design for proper system timing and synchronization of the interactions between system components such as PLL, DAC, ADC, and on-chip digital post-processing of ADC outputs. Digital post-processing will include down-sampling and decimation filter structures. Some examples of the synchronization that will be required are below:

• Knowledge of synchronization procedures and capabilities with synchronization tools for RFSoC systems
• Experience using Cadence design tools especially tools used for RFSoC timing such as Tempus Timing Signoff Solution and Quantus Extraction Solution. Experience with comparable tools from other vendors such as Synopsys is also acceptable, but final validation of all projects will use Cadence vendor tools.
• 3+ years of RFSoC design with focus on system timing and validation
• Multi-Tile Synchronization for multiple channels of DAC and ADC for phased array applications
• Clock distribution of a common clock within an RFSoC system and eventually across multiple RFSoC systems