Senior Manager, Package Design Engineering

Responsibilities:

• Lead package technology development and NPI execution, including R&D activities, coordination with global OSAT partners for new package development and product qualification, technology roadmap implementation, project budget tracking, and customer adoption programs.

• Manage the design and development of package and interconnect solutions for Renesas AI and data center infrastructure power products, including Smart Power Stages, Vertical Power Stages, Power Modules, and discrete FET packages.

• Support wide-bandgap SiC and GaN package development, DBC and AMB substrates, advanced interconnect technologies, wafer-level packaging, flip-chip, multi-chip modules, and power devices.

• Evaluate, select, and qualify materials, processes, assembly subcontractors (OSATs), and contract manufacturers in alignment with product requirements, quality standards, cost targets, and capacity needs.

• Partner with OSATs and contract manufacturers to plan and execute DOEs, optimize assembly processes, establish process specifications, and close technical gaps.

• Coordinate with Product Groups, Design, Applications, Quality, Operations, and Reliability teams to qualify new packages and processes within committed schedules.

• Drive resolution of package and process integration issues, ensuring robust process-window validation and risk assessment for critical manufacturing steps.

• Define and implement production controls, monitors, and corrective actions to prevent quality incidents and improve manufacturing robustness.

• Ensure smooth technology transfer into production and manage ramp-up monitoring, issue escalation, yield improvement, and readiness reviews.

• Work closely with OSATs and contract manufacturers to identify and resolve early-production process issues and ensure products meet quality, reliability, delivery, and customer requirements.

• Maintain strong technical expertise in power SiP/modules, wafer-level packaging, flip-chip interconnects, advanced substrates, and emerging power-package technologies, and translate industry developments into executable programs.

• Contribute to packaging roadmap development and lead execution of assigned technology and product-development programs, including schedules, resources, risks, and cross-functional deliverables.

• Lead technical response and corrective-action activities for internal and external customer concerns, partnering with Marketing, Product Groups, Quality, Operations, and Supply Chain teams.

• Establish, document, and maintain package design rules and engineering standards.

• Master’s or Bachelor’s Degree in Physics, Chemistry, Mechanical Engineering, Electrical Engineering, Materials Engineering, or a related discipline; doctorate is a plus.

• 12 to 15 years of relevant semiconductor package development experience, including technical or project leadership responsibility, with emphasis on power SiP/modules, wafer-level packaging, and flip-chip packaging.

• Strong understanding of power SiP/modules, wafer-level and flip-chip packaging methods, assembly processes, package and product qualification, reliability methods, SPC, DOE, and statistical analysis tools. Knowledge of wire-bonding, multi-chip modules, SiC/GaN packaging, and advanced substrates is preferred.

• Demonstrated ability to lead cross-functional technical teams, manage multiple development programs, influence global manufacturing partners, and elevate risks with clear recovery plans.

• Strong interpersonal, written, and verbal communication skills.

• Strong analytical, problem-solving, project management, and presentation skills.

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