Staff Engineer, SoC RTL Design

We are seeking an experienced engineer focused on Fabric and Memory Subsystem microarchitecture and RTL for high-performance SOCs. In this role, you will work on a server-class SoC fabric that supports cutting-edge data center designs.

This role is hybrid, based out of Toronto (ON), Ottawa (ON), Boston (MA), or Austin (TX).

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Design and develop the Fabric and Memory subsystems from scratch for a high-performance CPU, working closely with the DV, physical design, and architecture teams.
• Create RTL implementations in Verilog using both industry-standard tools and open-source infrastructure.
• Collaborate with cross-functional teams, including design, test, and post-silicon validation, to ensure seamless delivery of the Fabric and Memory subsystems.
• Evaluate and integrate 3rd-party IP components into the subsystem to meet performance and design goals.
• Optimize power, performance, and area (PPA) by working closely with performance modeling, DV, and physical design engineers to make informed trade-offs.
• Conduct experiments with RTL and analyze synthesis, timing, and power results to improve design quality.
• Debug complex RTL/logic issues across different design hierarchies (core, chip) in both pre-silicon and post-silicon environments.
• Enhance RTL design infrastructure and tools to streamline development and ensure consistency across projects.

Experience & Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with 5+ years of experience in Fabric or Memory subsystem design.
• Extensive experience with CPU and GPU fabrics, including cache coherence protocols and memory ordering models (e.g., MOESI).
• Strong understanding of interconnect topologies and protocols such as CHI, AXI, ACE, Tile Link. Die-to-die, Ethernet, and I/O protocols are also relevant.
• Proven ability to tightly couple memory subsystems with CPU cores, optimizing data paths, bandwidth, and latency to meet system requirements.
• Experience evaluating PPA trade-offs and working with synthesis, timing, and power tools to meet stringent design targets.
• Hands-on experience with hardware description languages (Verilog, System Verilog) and simulators like VCS, NC, and Verilator.
• Expertise in microarchitecture definition and specification development for complex memory systems.
• Strong debugging and problem-solving skills across hierarchical levels (core, fabric, and chip) in both pre- and post-silicon environments.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.