Senior Pre-Silicon Verification Engineer

Job Details

Intel's Central Engineering Group is seeking a Senior Pre‑Silicon Verification Engineer specializing in mixed‑signal verification to ensure complex analog and digital designs meet specification requirements before fabrication. This role focuses on developing comprehensive verification strategies for digital and mixed‑signal IP blocks, creating advanced behavioral models, and executing thorough verification plans that validate functional, performance, and power requirements across Intel's cutting‑edge semiconductor designs.

• Perform functional verification of digital and mixed‑signal logic components including analog behavioral modeling and advanced verification techniques (UVM, real‑number modeling, AMS simulation).
• Create verification environments that accurately model analog‑digital interactions and validate designs across process, voltage, and temperature (PVT) variations.

• Develop comprehensive IP verification plans, test benches, and scalable verification environments for mixed‑signal microarchitecture specifications.
• Build verification frameworks supporting regression testing, continuous integration, and both digital and analog verification flows.

• Execute verification plans, analyze power/timing/performance metrics, and conduct system‑level simulations and corner‑case analysis.
• Replicate, root‑cause, and debug complex issues in the pre‑silicon environment, implementing corrective measures to resolve failing tests.

• Collaborate with digital and analog architects, RTL developers, and physical design teams to meet functional, performance, and power goals.
• Document test plans, drive technical reviews, and maintain/improve verification infrastructure and methodology while ensuring smooth pre‑silicon to post‑silicon correlation.

The minimum qualifications listed below would be obtained through a combination of industry‑relevant job experience, internship experience, and/or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM related field of study.
• 5+ years of experience in digital design verification or mixed‑signal verification.
• 3+ years of experience with pre‑silicon verification environment architecture and development.
• Experience with complex mixed‑signal IP verification or system‑level verification.
• Experience in both digital verification methodologies (UVM/System Verilog).
• Perl, HTML, Python or similar scripting (Python preferred).

• Master's degree in Electrical Engineering, Computer Engineering, or a STEM related field of study.
• Experience with working in mixed‑signal design like Ser Des or PLLs.
• Experience with Ser Des PHY verification.
• Experience driving verification methodology changes and initiatives.
• Experience with Mixed Signal Verification (MSV).
• Experience with Gate Level Simulation (GLS).
• Experience with concepts of DFT, ATE, HVM.

• Competitive salary and comprehensive benefits package.
• Opportunity to work on Intel's most advanced mixed‑signal designs and technologies.
• Access to cutting‑edge mixed‑signal verification tools and simulation infrastructure.
• Collaboration with world‑class analog and digital design engineers and architects.
• Professional development opportunities in advanced mixed‑signal verification techniques.
• Direct impact on Intel's leadership in mixed‑signal semiconductor innovation.

Annual Salary Range for jobs which could be performed in Canada: CAD –
Salary range dependent on a number of factors including location and experience.

This role will require an on‑site presence. Job posting details (such as work model, location or time type) are subject to change.

Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find…