Principal Logic Design Engineer

Job Details:

Job Description:

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life.

About the Role
Intel's multiprotocol Ser Des design team is hiring in our Toronto office to ensure continued support of some of the world's most versatile next‑generation products. We have a long track record of silicon success over multiple technology nodes. Supporting the team in Toronto, we are hiring a technically experienced Principal Logic Design Engineer.

The key responsibilities of this person include the following:

Logic design, register transfer level (RTL) coding, analog circuit behavioral modeling and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.

Participating in the definition of architecture and microarchitecture features of the block being designed.

Applying various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

Reviewing the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

Supporting SoC customers to ensure high quality integration and verification of the IP block.

Driving quality assurance compliance for smooth IP SoC handoff.

Create design documentation

The Logic Design Engineer should possess the following attributes:

Excellent communication:
Expected to drive clarity across partners, managers.

Excellent teamwork:
With a relatively small team, we need everyone to help however and wherever they can.

Strong analytical and problem‑solving skills with the skills to independently draw conclusions.

Required

Skills and Experience:

Mixed‑signal design, specifically High‑Speed Ser Des design and architecture

Experience with PCS/FEC, gearbox, equalization, and clocking structures

Experience with pipelining, retiming, clock domain crossings (CDC), and latency optimization

Experience with post‑silicon validation and support of High‑Speed Ser Des IP

Experience working with automated Place‑and‑Route (APR) teamson synthesis, STA constraints, timing closure, and DFT considerations

Knowledge of FFE/DFE filters, CDR DSP blocks, interpolation/decimation, and adaptive algorithms

Reading and interpreting technical specifications to develop microarchitecture and implement RTL design in System Verilog

Excellent communication:
Expected to drive clarity across partners, managers.

Excellent teamwork:
With a relatively small team, we need everyone to help however and wherever they can

Preferred

Skills and Experience:

Familiarity with AXI, AHB, and APB protocols

DSP‑based CDR design, Forward Error Correction (FEC) coding, hardware/software co‑simulation, power/performance optimization, and machine learning‑assisted DSP tuning

Experience with PCIe, Ethernet (100G/400G/800G), CEI, USB, or similar standards

Scripting proficiency in at least one interpreted language (e.g., TCL, Perl, Python, Ruby)

Knowledge of UVM/testbench architecture, constrained random testing, and functional coverage

Qualifications:

Bachelor’s in electrical/computer engineering and 10+ years of experience
-OR
- Master’s degree with 6+ years of experience

Deep experience in Mixed signal design specifically High Speed Ser Des design and architecture

Job Type: Experienced Hire

Shift: Shift 1 (Canada) Primary

Location:

Canada, Toronto Additional Locations:
Business group:
The Central Engineering Group (CEG) is Intel's data‑driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).…