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Senior Analog Circuit Design Engineer - SerDes

Job in Toronto, Ontario, C6A, Canada
Listing for: Intel Corporation
Full Time position
Listed on 2026-02-17
Job specializations:
  • Engineering
    Electrical Engineering, Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 100000 - 125000 CAD Yearly CAD 100000.00 125000.00 YEAR
Job Description & How to Apply Below
Position: Senior Staff Analog Circuit Design Engineer - SerDes

Job Details

Shape the Future of High-Speed Connectivity

Are you passionate about pushing the boundaries of analog design? Join our elite Ser Des team and help architect the next generation of high-speed interconnect solutions that power tomorrow’s data centers, AI infrastructure, and communication networks.

As a Senior Staff Analog Design Engineer, you’ll be at the forefront of developing cutting‑edge analog and mixed‑signal circuits for blazing‑fast 112G and 224G Ser Des applications. This isn’t just another engineering role – it’s your opportunity to innovate, lead, and make a lasting impact on the semiconductor industry.

Why This Role?

  • Innovation at Scale:
    Work on industry‑defining technologies that enable global connectivity
  • Technical Excellence:
    Join a highly experienced team focused on breakthrough solutions
  • Career Growth:
    Opportunity to mentor others while expanding your own expertise
  • Collaborative Culture:
    Engage with brilliant minds across multiple disciplines
  • Impact:
    Your designs will power the infrastructure of tomorrow’s digital world

Ready to engineer the future of high‑speed communication? Join us in creating the analog circuits that will define the next decade of connectivity. This is more than a job; it’s your chance to leave a lasting mark on the semiconductor industry.

We’re looking for self‑driven innovators who thrive in collaborative environments and are passionate about pushing the limits of what’s possible in analog design.

What You’ll Do
  • Design high‑performance analog blocks and subsystems that define industry standards
  • Collaborate and lead alongside world‑class system architects, digital designers, and layout engineers
  • Validate and optimize post‑silicon validation and performance optimization initiatives
  • Mentor and guide the next generation of analog designers while providing technical leadership
  • Tackle complex challenges in high‑speed communication systems with creative solutions
  • Strong documentation and collaborative mindset to communicate effectively across teams
Minimum Qualifications
  • Master’s degree in electrical/electronic engineering or related field
  • 5+ years of proven experience in analog/mixed‑signal circuit design for high‑speed Ser Des
  • Experience in one or more domains: PLL, CDR, CTLE, DFE, ADC, or transmitter design
  • Standards knowledge: PCIe Gen4/Gen5 and Ethernet 100G/400G experience
  • Technical mastery of core analog design principles (noise, linearity, matching, stability)
  • Process expertise with advanced FinFET CMOS technologies
  • Tool proficiency:
    Cadence Virtuoso/ADE, HSPICE, or equivalent simulation platforms
  • Lab experience in silicon validation, measurements, and analog circuit debugging
Preferred Qualifications
  • Ph.D. in electrical/electronic engineering
  • 7+ years of specialized Ser Des analog design experience
  • Advanced knowledge of transmitter/receiver design, CDR loops, and equalization techniques
  • Experience with next‑gen standards: PCIe 6.0, 800G Ethernet, JESD exposure
  • Modeling expertise in Verilog‑A, MATLAB simulations, and automation scripting (Python, Tcl)
  • System understanding of signal integrity, channel modeling, and link analysis
  • Leadership qualities: cross‑functional collaboration and technical review contributions
Job Type

Experienced Hire

Shift

Shift 1 (Canada)

Primary Location

Canada, Toronto

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Annual Salary Range

CAD  –  (Canada)

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change.

Canada Accommodation

Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here.

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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Position Requirements
10+ Years work experience
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