Senior FPGA Design Engineer

Job Description

Why This Matters At Cognichip, we’re not just building AI - we’re redefining what’s possible at the nexus of silicon design and machine learning. As a Senior FPGA Design Engineer, you will be the hands‑on builder, fusing chip design expertise with ML to create the foundational blocks of our autonomous design flow. In this role, you won’t just design chips, you will create the libraries, IP and benchmarks that teach our AI how to design chips.

You will work alongside a cross‑functional team of world‑class engineers and researchers to translate hardware logic into artificial chip intelligence.

Senior FPGA Design Engineer

• Partner with ML and Software teams as a key hardware domain expert, translating complex silicon constraints into actionable insights for model training and agentic design
• Develop high‑quality RTL libraries, IP blocks and processor designs that serve as training data and composable parts of our environment
• Build and maintain an ecosystem of benchmarks and reference designs used to evaluate and increase the design velocity of our tools
• Execute and refine novel chip design methodologies, from architectural specs to synthesized netlists to complete bitstreams to identify where AI can optimize the flow
• Generate and curate massive datasets of syntactic and semantic hardware code to improve model robustness
• Implement robust verification environments, writing the System Verilog/UVM test benches and assertions with our tools that ensure our generated designs are correct‑by‑construction

• Bachelor’s or Masters in Computer Science, Electrical Engineering, or a closely related field
• 5-10 years of experience in RTL design, or a combination of design and verification
• Experience with AMD/Xilinx (Vivado, Vitis) and Altera/Intel (Quartus) ecosystems or ASIC physical design chains, including SoC and IP integrations
• Experience with hands‑on debugging - simulators, waveform viewing, coverage collection
• Knowledge of industry‑standard communication protocols (AXI, Ethernet, PCIe, DDR5, SPI, I2C, NoC, etc)
• Proficiency in System Verilog and Python for design and automation
• Excellent written and verbal communication skills, especially to convey chip design knowledge to software engineers and AI scientists
• Comfortable working in a dynamic, research‑heavy AI‑oriented startup environment

The following items are not required but are great bonuses:

• Personal projects showcasing innovation, creativity, and continuous learning
• Knowledge of open‑source tools and contribution practices (Verilator, CocoTB, Yosys, OpenSTA, etc)
• Experience with multiple areas of chip flow (RTL design, validation, synthesis, physical design, etc)
• Experience writing timing and other constraints (SDC, XDC, etc)
• Demonstrated coursework or project experience in machine learning and/or deep learning

We’re a fast‑moving AI startup with a collaborative, high‑trust culture. You’ll work with top‑tier engineers, scientists, and builders—solving hard problems that sit at the intersection of cloud computing, AI, and chip design. We value technical excellence, ownership, and the freedom to experiment. If you’re excited to build the future of engineering, you’ll feel right at home.

This position is available in Toronto. We believe a mindmeld between engineers and scientists leads to our professional growth and to great products; we have a hybrid schedule with four days in office, one day remote.

Don’t meet every single requirement? Feel over‑qualified? That’s okay—if you're excited about our mission, we’d still love to hear from you. We are growing fast and need a world class team of various experience levels.