Senior Analog Circuit Design Engineer - SerDes

Role Overview And Impact

Join Intel as a Senior Staff Analog Circuit Design Engineer – Ser Des and become instrumental in validating our industry‑leading Ser Des technologies. In this critical role, you’ll ensure our mixed‑signal designs meet the highest standards for reliability, functionality, and performance. Your technical expertise will directly influence product quality and strengthen Intel’s competitive edge in the semiconductor market. Working alongside diverse engineering teams, you’ll tackle sophisticated validation challenges, drive technological innovation, and shape the development of next‑generation hardware platforms.

This position offers an exceptional opportunity to create meaningful impact within Intel’s dynamic engineering organization while contributing to the future of technology.

• Design, develop, and implement comprehensive functional validation plans for industry‑leading Ser Des IP.
• Create and enhance validation frameworks while partnering with cross‑functional teams on design optimization, troubleshooting, and failure resolution.
• Conduct thorough root cause analysis and systematic debugging of mixed‑signal design failures and functional issues.
• Build and maintain post‑silicon validation workflows and status reports.
• Generate detailed validation reports documenting testing activities, outcomes, and improvement recommendations.
• Partner with architecture, design, verification, board, platform, and manufacturing teams to optimize debugging processes and validation methodologies for mixed‑signal interfaces.

• Exceptional analytical and problem‑solving capabilities for complex technical challenges.
• Outstanding collaboration and communication skills for effective cross‑functional teamwork.
• Passion for innovation combined with unwavering commitment to quality excellence.

- Intel is in the process of securing office space in the greater metropolitan area of Toronto, Ontario. This office will serve as your assigned work location in the future. Once the site is operational, your position will follow Intel’s hybrid work model, which currently requires on‑site presence at least four days per week. Until the office is ready, you will be classified as a remote employee and will be working virtually from the greater metropolitan area of Toronto, Ontario.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical discipline and 3+ years of relevant experience.
• 2+ years of experience in Ser Des post‑silicon validation and debug processes.
• Experience in I/O principles and mixed‑signal testing approaches.
• Experience in test planning, validation strategy formulation, and post‑silicon validation workflows.

• Post‑graduate degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• Experience with electrical validation and debugging of 224G+ Ser Des IP.
• Experience developing validation infrastructure and specialized testing tools.
• Programming experience with Python, C, C++.

Experienced Hire

Shift 1 (Canada)

Virtual Canada

The Central Engineering Group (CEG) is Intel’s data‑driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer‑driven, end‑to‑end solutions with short development cycles to deliver measurable business impact across Intel’s product and foundry businesses.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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