Principal Design Verification Engineer at Astera Labs

Astera Labs is seeking a Principal Design Verification Engineer to enhance their cutting-edge AI connectivity solutions. Bring your expertise in UVM and C/C++ to advance RTL simulation and co-simulation initiatives.

This role demands a strong foundation in electrical engineering, with at least eight years of experience focusing on complex SoC and silicon products in the Storage, Networking, or Server domains. You will utilize high-level programming within System Verilog environments and employ scripting tools to automate verification processes. This position is ideal for an entrepreneurial engineer ready to drive customer-focused solutions in a collaborative atmosphere.

Key Responsibilities:

• Develop test plans and sequences in UVM

• Integrate C/C++ within System Verilog using DPI/PLI

• Automate verification infrastructure with scripting tools

• Work with RTL designers to debug and analyze failures

• Create user-controlled constraints in verification methodologies

Requirements:

• Bachelor’s in Electrical Engineering, Master’s preferred

• 8+ years experience in SoC/silicon product development

• Professional attitude with multi-tasking abilities

• Capable of working independently and collaboratively

• Must be authorized to work in Canada immediately

Merge your verification expertise with Astera Labs to deliver unparalleled AI infrastructure solutions.
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