Analog and RF Layout Engineer

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities.

Where you can make a difference. Where no two days are the same.

As a Senior Analog / RF IC Layout Engineer, you will play a critical role in designing and enabling cutting‑edge high‑speed mixed‑signal silicon for next‑generation technologies. You will collaborate with world‑class design, verification, and process teams to deliver robust, scalable layouts in advanced FinFET nodes that power high‑performance products across industries.

This is a hybrid role based in Toronto, Canada.

• Lead and contribute to the physical layout of complex, high‑speed analog and RF mixed‑signal blocks from concept through tape‑out
• Develop and implement block‑level and chip‑level layouts in advanced CMOS FinFET technologies (7nm and below)
• Partner closely with analog, RF, and digital designers to ensure layout quality, performance, and manufacturability
• Own floor planning, block‑level routing, and top‑level chip assembly activities for complex integrated circuits
• Apply best‑in‑class layout techniques to address signal integrity, electromigration, thermal awareness, and high‑speed performance
• Drive layout reviews, layout verification, and design rule compliance using industry‑standard EDA tools
• Mentor and guide junior engineers while promoting quality, collaboration, and engineering best practices

• 6+ years of experience in Analog and RF IC layout for high‑speed applications
• Hands‑on experience developing and leading complex layouts at both block and full‑chip levels in advanced FinFET technologies (7nm and below)
• Strong expertise using industry‑standard EDA tools from Cadence, Mentor, and Synopsys
• Proven experience with layout of high‑performance analog mixed‑signal blocks, such as:
  • High‑speed transceivers
  • CMOS drivers
  • High‑speed data converters
  • PLLs
• Solid understanding of floor planning, routing, layer generation, thermal‑aware layout practices, and electromigration considerations

The base compensation range for this role in the posted location is: $70,751 to $165,984- CA.

Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law.

The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction.

These may include, but are not limited to:
Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity.

It is not typical for candidates to be hired at or near the top of the posted compensation range.

In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws.

• Paid time off based on employee grade (A-F), defined by policy:
  Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave

• Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)
• Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
• Life and disability insurance
• Employee assistance programs
• Other benefits as provided by local policy and eligibility

Capgemini is an Equal Opportunity Employer…