Senior Memory Controller Verification Engineer

Responsibilities

• Develop verification infrastructure (test benches, BFMs, checkers, monitors, randoms)
• Come up with, review and drive test plan execution for planned features
• Understand the performance requirements of your IP, come up with, review and drive performance testplan for your IP
• Ensure code and functional coverage of all the RTL which you will verify
• Work with and enable FPGA and software teams to ensure that software is tested
• Plan for and be involved with post-silicon verification and debug

• BS / MS or equivalent experience
• 3+ years of ASIC verification experience of complex design units, displaying good attention to detail, teamwork, problem solving and success
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Background with System Verilog and UVM based methodology for ASIC verification

• Strong C/C++ programming experience
• Prior Design or Verification experience of dynamic memory controllers (ddr2, ddr3, ddr4, ddr5, lpddr2, lpddr3, lpddr4, lpddr5, lpddr6)
• Strong debugging and problem solving skills
• Scripting knowledge (Python/Perl/shell)
• Good interpersonal skills and ability & desire to work as part of a team

The base salary range is 125,000 CAD - 175,000 CAD for Level 3, and 155,000 CAD - 205,000 CAD for Level 4. You will also be eligible for equity and benefits.