Verification Engineer Position

Position: Astera Labs Verification Engineer Position
Join Astera Labs as a Verification Engineer and apply your expertise in C/C++ and UVM to improve cutting-edge AI infrastructure solutions.

Your role will focus on enhancing verification processes for SoC products.
We are seeking a Principal Design Verification Engineer with over eight years of experience in complex silicon product development. You must be adept in UVM and System Verilog environments while employing high-level programming languages for RTL simulation and emulation. Your professional experience will enable you to prioritize multiple tasks effectively and work collaboratively with minimal guidance.

Key Responsibilities:

• Integrate C/C++ in System Verilog using DPI/PLI

• Develop and execute UVM-based test plans

• Utilize scripting tools to automate processes

• Work independently with RTL designers on debugging

• Implement transaction-based verification methods
Requirements:

• Bachelor’s in Electrical Engineering; advanced degree preferred

• 8+ years of relevant SoC experience

• Strong problem-solving abilities

• Familiarity with PCI-Express, Infiniband

• Experience with verification IP and automation
Bring your extensive verification expertise to Astera Labs, driving innovation in connectivity solutions.
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