Sr. Design Verification Engineer

2 days ago Be among the first 25 applicants

This range is provided by Arcadia. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

CA$/yr - CA$/yr

Location:

Hybrid – Downtown Toronto (4 days/week in office, near Union Station)

Type:
Full-time | Permanent

Compensation: $150K–$200K CAD base + early-stage equity

A well-funded AI + semiconductor startup ($30M+ raised) is hiring a junior/intermediate Design Verification Engineer to help reinvent chip verification through AI-native tooling and intelligent automation.

This is a rare chance to get in early, work alongside senior silicon engineers and ML researchers, and build your career on greenfield verification flows that combine traditional System Verilog/UVM with cutting-edge AI-driven design tools.

• Write and run System Verilog/UVM test benches to validate RTL blocks.
• Develop directed and constrained-random tests for functional coverage.
• Work with senior DV/RTL engineers to define verification plans and metrics.
• Automate test execution, regressions, and coverage collection with Python/scripting.
• Contribute to experiments in AI-assisted verification workflows.

• 1–5 years in ASIC/FPGA verification or chip design internships/projects.
• Familiarity with System Verilog, UVM, or similar verification methodologies.
• Strong scripting skills (Python, TCL, or Shell) for automation.
• Solid fundamentals in digital design, RTL, and computer architecture.
• Eager to learn and thrive in a fast-paced startup with strong mentorship.
• Hands-on coursework or internships with EDA tools (VCS, Questa, Xcelium, etc.).
• Exposure to open-source verification frameworks (CocoTB, Verilator).
• Knowledge of on-chip protocols (AXI, SPI, PCIe, DDR).
• Coursework or curiosity around AI/ML in chip design.