Static Timing Analysis; STA Engineer

Altera is seeking a Static Timing Analysis (STA) Engineer to support timing closure and analysis for advanced FPGA designs. This role will focus on executing timing analysis, debugging violations, and partnering with cross‑functional teams to deliver high‑performance, power‑efficient designs. The ideal candidate has a strong foundation in STA, experience with modern design flows, and the ability to work effectively in a collaborative engineering environment.

• Perform static timing analysis for FPGA designs, including setup/hold checks, constraint validation, and timing sign‑off support.
• Identify, debug, and resolve timing violations in collaboration with RTL, synthesis, and physical design teams.
• Assist in developing and validating timing constraints to ensure accurate modeling of design intent.
• Work closely with design, architecture, and implementation teams to improve timing convergence.
• Apply established STA methodologies and contribute to flow improvements and automation where applicable.
• Support optimization efforts for performance, power, and area (PPA) through timing‑driven analysis.

Estimated Salary Range: $102.9K – $149.1K CAD. Compensation includes base salary and performance‑based incentives.

• 6+ years of experience in Static Timing Analysis (STA) for ASIC or FPGA designs.
• Solid understanding of STA fundamentals (setup/hold, timing paths, clocking, CDC basics).
• Experience with industry‑standard tools (e.g., Prime Time or equivalent).
• Familiarity with synthesis and place‑&‑route flows.
• Working knowledge of RTL design (Verilog/System Verilog) and FPGA or ASIC design methodologies.
• Ability to analyze timing reports, identify root causes, and propose actionable solutions.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Preferred: experience with FPGA architectures and timing flows, familiarity with advanced process nodes or high‑speed designs, scripting experience (e.g., Tcl, Python) for automation, exposure to large‑scale or distributed engineering environments.

Job Type: Regular.

Shift: Shift 1 (Canada). Primary

Location:

Toronto, Ontario, Canada.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation or ordinance.