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Senior ASIC Verification Engineer, Coherent Speed Interconnect

Job in Toronto, Ontario, C6A, Canada
Listing for: NVIDIA AI
Full Time position
Listed on 2026-07-21
Job specializations:
  • Engineering
    Test Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 125000 - 175000 CAD Yearly CAD 125000.00 175000.00 YEAR
Job Description & How to Apply Below
Position: Senior ASIC Verification Engineer, Coherent High Speed Interconnect

We are now looking for a Senior ASIC Verification Engineer for our Coherent High Speed Interconnect team! For two decades we have pioneered visual computing, the art and science of computer graphics. Our invention of the GPU has driven growth in video games, movie production, product design, medical diagnosis, and scientific research.

Today we are at the beginning of the next era—AI computing—enabled by GPU deep learning. As an ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our innovative high‑speed coherent interconnects for mobile SoCs and GPUs, contributing to product lines ranging from consumer graphics to self‑driving cars and AI.

Responsibilities
  • Verify the design and implementation of high‑speed coherent interconnects, architectures, and golden models.
  • Architect micro‑architecture using sophisticated verification methodologies.
  • Develop verification infrastructure (test benches, BFMs, checkers, monitors), define scope, create test/coverage plans, and validate design correctness in collaboration with architects, designers, emulation, and silicon verification teams.
Qualifications
  • Bachelor’s or Master’s Degree (or equivalent experience).
  • 3+ years of relevant verification experience.
  • Experience designing testbench environments for unit‑level verification.
  • Background in verification using random stimulus, functional coverage, and assertion‑based verification methodologies.
  • Prior design or verification experience of coherent high‑speed interconnects.
  • Knowledge of industry‑standard interconnect protocols such as PCIe, CXL, CHI.
  • Strong background developing test benches from scratch using SV and UVM methodology.
  • Experience with C++ programming, scripting, and System Verilog.
  • Exposure to design and verification tools (VCS or equivalent simulation tools) and debugging tools (e.g., Debussy, GDB).
  • Strong debugging and analytical skills.
  • Excellent communication and interpersonal skills, with a history of mentoring junior engineers and interns.
Salary and Benefits

Base salary ranges from 125,000 CAD to 175,000 CAD for Level 3, and 155,000 CAD to 205,000 CAD for Level 4. You will also be eligible for equity and additional benefits.

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Position Requirements
10+ Years work experience
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