Senior ASIC Verification Lead - SystemVerilog/UVM, Ethernet
Job Description & How to Apply Below
HCL Technologies Limited is seeking an experienced verification engineer to lead and contribute to the verification of multiple ASIC blocks using UVM-based environments. You will develop sequences, tests, and debug strategies while driving coverage closure and end-to-end verification across assigned blocks.
The role requires strong System Verilog/UVM skills and hands-on experience with PCIe, UCIe 2.0, and Ethernet protocols.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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