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Staff Engineer, Physical Design​/Implementation

Job in Toronto, Ontario, C6A, Canada
Listing for: Socket.dev
Full Time position
Listed on 2026-08-13
Job specializations:
  • Engineering
    Hardware Engineer, Systems Engineer, Test Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 173000 - 243000 CAD Yearly CAD 173000.00 243000.00 YEAR
Job Description & How to Apply Below

Company:
Qualcomm Canada ULC Job Area:
Engineering Group, Engineering Group > ASICS Engineering

General

Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

You will lead and drive physical design implementation for complex, large-scale retimer-class and full-reticle ASIC products in advanced technology nodes. This role requires strong technical leadership to synthesize ambiguous requirements, drive execution across cross-functional teams, and deliver high-quality silicon meeting aggressive power, performance, and area (PPA) targets.
Replacement Position

What You'll Do

  • Lead and execute end-to-end Physical Design flow for SoC and retimer ASICs, including:
    • Floor planning
    • Clock Tree Synthesis (CTS)
    • Placement & Routing
    • Power Delivery Network (PDN)
    • Timing analysis and closure
  • Plan and implement full-chip or hierarchical designs, including full-reticle-scale integration
  • Drive timing closure across all corners and modes (MMMC), including SI-aware optimization
  • Perform and review physical verification checks:
    • DRC, LVS
    • Design-for-manufacturability (DFM)
    • Design-for-yield (DFY)
  • Collaborate with cross-functional engineering teams (front-end, analog/Ser Des, DFT, packaging, silicon validation) to ensure design convergence and tapeout readiness
  • Lead integration of high-speed Ser Des macros and mixed-signal IP, ensuring robust floorplan and signal integrity alignment
  • Drive IR/EM closure, power optimization, and congestion mitigation for large die designs
  • Provide schedules, risk assessment, and execution tracking to drive successful silicon tapeouts
  • Act as a strong technical contributor in design reviews and project meetings, influencing architecture and implementation decisions
  • Develop and improve physical design methodologies and flows to enhance efficiency and scalability

What You'll Need:

  • Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of experience, OR Bachelor’s degree and 4+ years of progressive experience in ASIC Physical Design or related domain
  • Strong experience with
    :
    • End-to-end ASIC Physical Design flow
    • Timing closure and signoff methodologies
    • Physical verification flows
  • Hands-on expertise in industry-standard EDA tools (e.g., Cadence Innovus / Synopsys ICC2)
  • Solid understanding of:
    • Power delivery and reliability (IR/EM)
    • Clocking architectures and CTS
    • Large-scale SoC integration challenges

Preferred Qualifications

  • Experience with high-speed Ser Des / retimer designs (PAM4-class signaling)
  • Experience with full-reticle or near-reticle SoC implementation
  • Familiarity with multi-die / chiplet / advanced packaging architectures
  • Exposure to data center, networking, or optical connectivity ASICs
  • Strong scripting and automation skills (Python, Tcl)

Key Competencies

  • Proven ability to lead complex PD execution in high-pressure tapeout environments
  • Strong analytical and problem-solving skills with attention to detail
  • Ability to synthesize ambiguous or conflicting requirements into execution plans
  • Effective collaboration across global, cross-functional engineering teams

Minimum Qualifications:

  • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Applicants
:
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disabili or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.

Qualcomm is also…

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