DSP Systems Engineer, Staff

General

Summary:

Qualcomm is a global leader in semiconductor and wireless technology, with a decades-long track record of delivering silicon that defines industry standards. Our Ser Des IP is deployed at hyperscale across the world's most demanding data infrastructure — giving engineers on this team rare access to real-world deployment feedback, cutting-edge process nodes, and a deep bench of domain expertise that few organizations can match.

New Position

High-speed Ser Des is the backbone of modern data infrastructure. As AI workloads, cloud computing, and hyperscale networking continue to scale, the demand for faster, more power-efficient interconnects has never been greater — and our team is at the center of it. Our High-Speed Ser Des DSP group builds the DSP engines that power PCIe, 112G and 224G Ser Des solutions deployed across the world's leading data centers, networking platforms, and next-generation connectivity products.

We operate at the intersection of theory and silicon — from architecture and algorithm design through bring-up and customer deployment. We're a close-knit team that values both technical depth and collaborative problem solving. The work is demanding and the pace is fast, but we tackle hard problems together, and we take pride in delivering solutions that are technically rigorous and practically impactful.

We're looking for a Staff DSP Systems Engineer who brings strong technical fundamentals, a methodical approach to problem solving, and a genuine passion for high-speed signal processing. You'll work closely with a team of specialists across DSP, RTL, Firmware, and Post-Silicon disciplines — contributing to algorithm development, model building, diagnostic tooling, and silicon validation on some of the most technically challenging Ser Des problems in the industry.

High performers naturally grow into ownership across DSP subsystems and become trusted technical voices on the team. This is a role for engineers who want to develop deep expertise, collaborate with talented peers, and build solutions that ship in real products at global scale.

• Design and refine high-speed DSP Ser Des features and architectures in collaboration with RTL/Firmware designers; actively participate in implementation and design reviews.
• Develop and maintain bit-accurate and cycle-accurate MATLAB models for RTL verification, pre-silicon performance estimation, and post-silicon correlation.
• Research and analyze DSP algorithms addressing power, performance, and area trade-offs across equalization, LMS adaptation, CDR, noise mitigation, linearity, and related topics across the full DSP signal chain.
• Develop and analyze DSP diagnostic features and performance metrics — including SNR, eye monitoring, BER floor, linearity, and jitter — to proactively identify design limitations and drive continuous improvements.
• Partner with Firmware, DV, and Post-Silicon teams by providing clear theory of operation documentation, pseudocode, and DSP sequences to support product bring-up, regression testing, and post-silicon lab debug.

• Strong proficiency in MATLAB, Python, and C/C++; embedded firmware experience strongly desired.
• Solid RTL and digital design fundamentals — comfortable driving simulations, participating in code reviews, and debugging failures with a systematic, methodical approach.
• Proven DSP architecture experience in mixed-signal Ser Des, including adaptation/calibration, clocking, equalization, and FEC — with the depth to understand where theory meets its limits in silicon.
• Skilled in developing DSP diagnostic tools and analyzing performance metrics — BER, SNR, jitter, eye characterization — to isolate root causes and support team-wide debug and resolution efforts.
• Solid grasp of post-silicon debug, voltage/temperature effects on performance, analog continuous-time circuits, ADCs, and noise/transfer function analysis.
• Strong cross-functional collaboration skills — able to work effectively across RTL, Firmware, DV, and Post-Silicon teams, contribute constructively in technical discussions, and build consensus around complex engineering trade-offs.
• Clear and…