Verification Engineer I for ASIC Projects

Join a top-tier client's innovative team as a Verification Engineer I specializing in Logic/Mixed-Signal verification. Focus on ASIC verification and collaborate extensively for optimal results.

In this role, you will contribute to the verification of complex mixed-signal SoCs and ASIC designs. You'll develop verification plans and collaborate with architecture and design teams to ensure product excellence. Your responsibilities will also extend to timing analysis, debugging, and creating effective automation tools within mixed-signal design frameworks.

Key Responsibilities:

• Create verification plans and test strategies

• Execute and analyse static timing analysis for designs

• Validate analog circuits and perform comprehensive mixed-signal simulations

• Resolve complex issues in verification environments

• Develop automation solutions for improved productivity

Requirements:

• BSEE, BSCE or equivalent; MS preferred

• 1-5 years in related semiconductor design roles

• Strong experience with System Verilog/Verilog

• Familiar with RTL tools and verification methodologies

• Proven debug and problem-solving capabilities

Drive ASIC projects forward by ensuring verification excellence and cross-disciplinary collaboration.
#J-18808-Ljbffr