Entry-Level Mixed-Signal Verification Engineer

Launch your career with a premier client as an Entry-Level Verification Engineer I. This opportunity emphasizes Logic and Mixed-Signal verification within complex designs.

As a Verification Engineer I, your role includes the development of verification plans and execution of timing analysis for mixed-signal systems. Working closely with various teams, you will tackle challenges in verification methodologies and ensure design quality through comprehensive testing and collaboration. You'll also enhance simulation efficiency through automation and innovative problem-solving.

Key Responsibilities:

• Develop verification requirements from product specifications

• Conduct static timing analysis and close timing gaps

• Validate analog circuit designs through testing and simulation

• Investigate design issues across various domains

• Optimize verification processes using automation tools

Requirements:

• BSEE, BSCE, or equivalent; MS preferred

• 1-5 years experience in ASIC verification

• Proficiency in System Verilog/Verilog and scripting tools

• Understanding of timing analysis techniques

• Strong collaboration and communication skills

Embark on your verification engineering journey, ensuring quality in innovative designs.
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