Chip-Scale Packaging Engineer; GaN​/SiC)

Navitas Semiconductor seeks a Staff Electromechanical Packaging Engineer in Torrance, CA. You will contribute to chip-scale packaging design, HDI substrates, and cross-functional collaboration with layout, ASIC design, and manufacturing teams.

The role requires a BS in mechanical or electrical engineering, 3+ years in microelectronics packaging or PCB design, and familiarity with CAD tools and thermal analysis.

This opening is for the Staff Chip-Scale Packaging Engineer (GaN/SiC) role at Navitas Semiconductor Usa.

For the Staff Chip-Scale Packaging Engineer (GaN/SiC) position at Navitas Semiconductor Usa, we are reviewing applications now.

Step into the Staff Chip-Scale Packaging Engineer (GaN/SiC) role at Navitas Semiconductor Usa in Torrance, CA, United States and grow with us.

Please review the full job details above before applying.

If your experience matches this role, we encourage you to apply.