Principal Digital Design Engineer

Job Details:

Job Location:

Torrance, CA - Torrance, CA, Position Type:
Full Time, Salary Range: $170000.00 - $190000.00

Salary/year,

Job Purpose:

Navitas Semiconductor (Nasdaq: NVTS) is a next-generation power semiconductor leader driving innovation ingallium nitride (GaN) andhigh-voltage silicon carbide (SiC) technologies. Our products enable faster, more efficient power delivery acrossAI data centers, high-performance computing, energy and grid infrastructure, and industrial electrification.

With more than 30 years of combined expertise in wide bandgap technologies, GaNFast™ power ICs integrate GaN power, drive, control, sensing, and protection, delivering faster power delivery, higher system density, and greater efficiency. GeneSiC™ high-voltage SiC devices leverage patented trench-assisted planar technology to provide industry-leading voltage capability, efficiency, and reliability for medium-voltage grid and infrastructure applications.

We are seeking aPrincipal Digital Design Engineer to join our fast-growing, collaborative team. The ideal candidate is self-motivated, energetic, and able to thrive in a high-growth, innovative environment, contributing directly to technologies that are shaping the future of power electronics.

• Design and implement digital blocks for ASICs using Verilog/System Verilog and standard ASIC design flows.
• Participate in pre-silicon simulation and verification using Cadence tools and standard cell libraries.
• Develop and maintain UVM/System Verilog test benches, including functional coverage models, assertions (SVA), and constrained-random stimulus.
• Own coverage closure: analyze code and functional coverage, find gaps, and drive improvements in existing verification suites.
• Apply formal verification where it fits, such as property checking, connectivity, and register and FSM verification.
• Build mixed-signal verification using real-number modeling or AMS co-simulation to verify digital-analog interactions.
• Support ASIC tape-out activities, including synthesis, static timing analysis, and design signoff.
• After silicon returns from the foundry, focus on developing FPGA-based test builds (using Xilinx tools) to validate and characterize fabricated PMIC silicon.
• Interface and integrate digital control logic with analog/mixed-signal blocks commonly found in power management applications.
• Own digital architecture specs from product requirements through tape-out.
• Lead design and verification reviews, and follow coding, verification, and methodology standards set by the team.
• Mentor junior engineers and provide technical direction across multiple projects.
• Lead post-silicon debug and root-cause analysis, and feed silicon learnings back into design and verification.
• Evaluate and improve design and verification flows and tools to increase team productivity and reuse.
• Write and maintain automation scripts for regression testing, build flows, and hardware validation.
• Collaborate with cross-functional teams including analog designers, layout, validation, and test engineers to ensure robust and reliable PMIC design.

• Digital design principles: synchronous/asynchronous design, FSMs, clock-domain crossing, reset strategies, and low-power techniques.
• ASIC flow from start to finish: RTL, synthesis, STA, DFT, equivalence checking, place and route handoff, and signoff.
• Verification methodology: SVA, functional and code coverage, constrained-random testing, and formal verification concepts.
• PMIC and power electronics basics: DC-DC converter control, sequencing, protection and fault handling, trimming, and how digital logic interacts with analog blocks.
• Mixed-signal modeling and co-simulation concepts.
• Serial…