SerDes Speed PHY Validation Engineer

Position: SerDes & High-Speed PHY Validation Engineer
About the Role
We are looking for a motivated Ser Des & High-Speed PHY Validation Engineer to join our high-speed connectivity validation team and contribute to the development of next‑generation Ethernet networking solutions for cloud, AI, and data center applications.

In this role, you will participate in the validation and characterization of advanced Ethernet Ser Des technologies spanning 112G PAM4 and next generation 224G PHY architectures. You will work closely with validation, design, signal integrity, and system teams to ensure robust and compliant high‑speed communication solutions from first silicon bring‑up through product readiness.

This opportunity is ideal for engineers who enjoy hands‑on lab work, high‑speed measurements, signal integrity challenges, and collaboration across multiple engineering disciplines.

What You'll Do
Perform Ser Des Validation and Characterization

Execute validation activities for high‑speed Ethernet Ser Des and PHY solutions across silicon, package, board, and system environments.

Perform characterization testing to evaluate performance, robustness, and design margins across operating conditions.

Support silicon bring‑up and debug activities.

Contribute to root‑cause investigations and issue resolution.

Execute Advanced High‑Speed Measurements
Perform and analyze:

Eye‑diagram measurements

BER and margin analysis

Bathtub curve characterization

Jitter decomposition (RJ, DJ, TJ)

CTLE and DFE performance evaluation

TX FIR optimization

Channel loss and equalization analysis

Debug Signal Integrity Challenges
Assist in investigating performance limitations across:

Silicon

Package

PCB channels

Connectors

Cables

End‑to‑end system interconnects

Work closely with design and architecture teams to support technical investigations and design improvements.

Validation Automation

Work with existing validation and data‑analysis frameworks to improve test efficiency and coverage.

Contribute to automation solutions supporting test execution, data collection, analysis, and reporting.

Participate in developing tools that improve lab productivity and debug efficiency.

Work with Industry‑Leading Test Platforms
Configure and operate advanced high‑speed validation equipment, including:

BERTs

High‑speed oscilloscopes

Arbitrary waveform generators (AWGs)

Jitter injection systems

Channel emulators

Vector network analyzers (VNAs)

Collaborate Across Engineering Teams
Work closely with:

Ser Des and PHY design teams

SI/PI engineers

Package and board‑design teams

System and validation engineers

Drive Standards Compliance
Support compliance and interoperability testing according to industry standards, including:

IEEE 802.3cd

IEEE 802.3ck

IEEE P802.3dj

Document and Communicate Results

Document validation procedures and test results.

Prepare clear technical summaries and reports.

Present findings and recommendations to team members and stakeholders.

Required Qualifications

2+ years of experience in Ser Des validation, PHY validation, signal integrity, or related high‑speed design environments.

Experience working with high‑speed communication systems.

Understanding of:

PAM4 signaling

BER measurements

Jitter analysis fundamentals

Equalization concepts (CTLE, DFE, FFE)

Signal integrity principles

Experience using laboratory equipment such as oscilloscopes, BERTs, VNAs, or similar instruments.

Strong analytical and debugging skills.

Ability to work effectively in a collaborative engineering environment.

B.Sc. or M.Sc. in Electrical Engineering or a related field.

Preferred Qualifications

Experience with Ethernet Ser Des validation.

Experience with 112G PAM4 technologies.

Familiarity with 224G Ser Des technologies.

Familiarity with Ethernet and IEEE specifications.

Experience with compliance and interoperability testing.

Experience with Keysight…