Sr Mgr R&D​/Product Dvl Engineering

At TE, you will unleash your potential working with people from diverse backgrounds and industries to create a safer, sustainable and more connected world.

We are seeking an experienced engineering leader to manage our integrated Hardware and Signal Integrity organization for high-speed external cable assemblies. The role owns the engineering lifecycle from architecture, simulation, hardware and PCB design through bring-up, qualification, production support, and customer issue resolution. The manager will drive passive and active copper solutions across OSFP, QSFP-DD (QDD), QSFP, OSFP-XD, CDFP, breakout, and emerging high-density form factors for Ethernet, AI infrastructure, and PCIe applications.

• External cable assembly platforms using OSFP, QSFP-DD (QDD), QSFP, OSFP-XD, CDFP, and future high-density form factors.
• Passive Direct Attach Copper (DAC), redriver-based Active Copper Cable (ACC), and retimer-based Active Electrical Cable (AEC) architectures.
• High-speed electrical channels supporting 112G, 224G, and future 448G and beyond lane-rate technologies, including Ethernet and PCIe applications.
• End-to-end design considerations spanning connector and paddle-card interfaces, cable performance, PCB routing, power integrity, EMI/EMC, thermal management, firmware interfaces, and system interoperability.

• Lead global Hardware, PCB Design, and Signal Integrity engineering teams across passive and active external cable products.
• Own electrical architecture, hardware design, SI/PI analysis, PCB implementation, and design verification.
• Drive ACC development using linear redriver technology, including equalization strategy, power delivery, thermal performance, and link-margin optimization.
• Drive AEC development using retimer technology, including Ser Des architecture, clocking, power and thermal design, device integration, firmware interfaces, and end-to-end interoperability.
• Manage form‑factor implementation and design trade‑offs for OSFP, QSFP-DD (QDD), QSFP, OSFP-XD, CDFP, breakouts, and new platform concepts.
• Drive products from concept and simulation through prototype bring‑up, qualification, customer validation, and production release.
• Establish common design rules, simulation methodology, technical standards, design reviews, and reusable engineering assets.
• Improve correlation among simulation, S‑parameter measurements, laboratory characterization, and system‑level BER/FEC performance.
• Handle and support root‑cause investigations for complex hardware, SI, EMI, thermal, manufacturing, and customer issues.
• Partner with Product Management, IC suppliers, Firmware, Software, Validation, Manufacturing, Quality, Sourcing, and customer engineering teams.

• BS or advanced degree in Electrical Engineering or a related discipline.
• 12+ years of relevant engineering experience, including 5+ years in technical or people leadership.
• Strong expertise in high‑speed hardware design, signal and power integrity, PCB design, channel modeling, S‑parameters, Ser Des, and laboratory characterization.
• Hands‑on understanding of DAC, redriver‑based ACC, and retimer‑based AEC product architectures.
• Experience with OSFP, QSFP-DD, QSFP, OSFP‑XD, CDFP, or comparable high‑speed pluggable and cabled I/O form factors.
• Experience spear heading complex products from architecture through qualification and production, preferably within Ethernet, AI infrastructure, networking, or PCIe ecosystems.
• Demonstrated ability to lead global teams and work across engineering, operations, suppliers, and customer‑facing organizations.

#TANAUV

SET :
Strategy, Execution, Talent (for managers)

TE Connectivity plc (NYSE: TEL) is a global…