Senior FPGA Design Engineer - Onsite Tucson, AZ

** Date Posted:
**** Country:
** United States of America
*
* Location:

** AZ852: RMS AP Bldg M02 1151 East Hermans Road Building M02, Tucson, AZ, 85756 USA
** Position Role Type:
** Onsite
* * U.S. Citizen, U.S. Person, or Immigration Status Requirements:
** Active and transferable U.S. government issued security clearance is required prior to start date. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance
** Security Clearance:
** DoD Clearance:
Secret At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world.

The
** Effector Digital Products** (EDP) department develops electronics for our weapon system products. We are responsible for the architecture, design, and documentation of deliverable FPGA embedded processing. We engage at the outset of the weapon system development and follow our designs through deployment. Our products are deployed all over the world, from the ground to exoatmospheric environments and into space.
As a
** Senior FPGA Design Engineer
** you will develop FPGA designs for all major vendors and device families including:
Xilinx, Altera, and Microsemi. Designs are implemented using VHDL for the following applications: gigabit serial interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces.

Designers work with circuit card designers and systems engineers to develop requirements, architect new parts, collaborative modeling of algorithms, partition and perform code development, simulation, and place and route. Designs are verified against requirements using both directed test and constrained random methodologies. Design support is expected from requirements definition through integration and test. Design documentation and configuration management are required.

This position is
** 100% ONSITE
** in Tucson, Arizona.

** What You Will Do
*** Design and deliver production quality FPGA releases from initial proof of concept up to production
* Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)
* Translate system level requirements into FPGA requirements
* Design and code in VHDL for reliability and maintainability
* Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage
* Help drive projects and execute to program schedules on time and budget
* Create complete documentation including requirements, verification plan, and user’s guides
* Lead small teams and mentor junior engineers
* Support internal and external technical reviews
** Qualifications You Must Have
*** Bachelor’s Degree in Electrical Engineering, Computer Engineering or Electrical Engineering Technology
* A minimum of 5 years of experience to include the following:  + FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)  + Xilinx or Microsemi devices and flow tools  + Delivering FPGA/ASIC solutions to system level applications  + Hands on experience with integration and debug of FPGA/ASIC devices
* The ability to obtain and maintain a US security clearance
** prior to the start
** date. U.S. citizenship is required as only U.S. citizens are eligible for a security clearance
* Ability to obtain
** Interim Secret
** U.S. government issued security clearance is required
** prior
* * to start date.
** Qualifications We Prefer
*** FPGA/ASIC design experience in one or more of the following areas:  + Radar processing techniques  + Image processing techniques for visual and infrared sensors  + Embedded systems design using ARM, Microblaze, or Nios processors  + Gigabit serial interfaces and multi-gigabit transceivers (MGTs)  + Constrained random verification in UVM using System Verilog  + Verification utilizing emulation platforms,…