HWIL Sr Systems Integrator - FPGA Emphasis - P3

HWIL Sr Systems Integrator - FPGA Emphasis - P3

Join to apply for the HWIL Sr Systems Integrator - FPGA Emphasis - P3 role at Raytheon
.

Date Posted
:

Country
:
United States of America

Location
: AZ805: RMS AP Bldg 805 1151 East Hermans Road Building 805, Tucson, AZ, 85756 USA

Position Role Type
:
Onsite

U.S. Citizenship and Security Clearance Requirements
:
Active and transferable U.S. government‑issued security clearance is required prior to the start date. U.S. citizenship is required for eligibility to obtain a security clearance.

Security Clearance
:
DoD Clearance:
Secret

At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world.

Raytheon is seeking a Hardware in the Loop (HWIL) Senior Systems Integrator with FPGA experience. The role requires development and integration of FPGA solutions across multiple programs. After FPGA delivery and integration, the candidate will continue systems integration tasks including, but not limited to, hardware/software/FPGA interfacing, radar and video emulation, and missile electronics interfacing. The candidate should have FPGA design experience within a multidisciplinary team and experience troubleshooting both low‑level and systemic issues.

The candidate should also have experience with software/FPGA interfacing, and both board and system‑level integration. The candidate will own the responsibility from requirements to completion of integration for all FPGA projects that they own.

• Develop FPGA solutions across multiple HWIL projects.
• Coordinate and collaborate within the common department FPGA team and team lead (including other SMEs) to best achieve the needs of our support projects.
• Help other FPGA developers on the team, particularly those who are new to development.
• Produce FPGA‑level requirements that meet system‑level requirements.
• Track execution and report status to program stakeholders.
• Report on the status of metrics to stakeholders.
• Development and sustainment activities such as:
• Code reviews and pull requests using Git.
• Developing constraints and rudimentary experience with device timing closure.
• Creating self‑testing and reporting simulations.
• Adhering to configuration and code‑management tools such as Git.
• Developing common code and scripting to decrease development time on future efforts.
• Integrating with software, hardware, and system engineers on a multidisciplinary team.

• Radar timing, parameters, and stimulation of missile hardware, including both intermediate frequency (IF) and radio frequency (RF).
• Video injection into missile hardware and systemic understanding of multiple missiles and interceptors.
• Knowledge of navigation and targeting.
• Opportunity to learn system engineering, software development, and other skills in a multi‑disciplined department.

• Typically requires a Bachelor’s Degree in Science, Technology, Engineering or Mathematics (STEM) and 5 years of relevant experience.
• Experience examining FPGA vendor documentation and circuit board schematics to find information related to FPGA development, FPGA tool use, and integration.
• Experience with FPGA timing closure, coding best practices, and build‑tool flow.
• Active and transferable U.S. government‑issued Secret security clearance (not interim) is required prior to the start date. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance.

• Strong communication skills.
• Experience in the following:
• FPGA development, including requirements, implementation, and solving low‑level and systemic issues.
• Implementation of basic interfaces such as UART, I2C, and/or SPI.
• Vivado Block Designer or another FPGA vendor equivalent.
• FPGA testing and system integration.
• Self‑checking simulations.
• Git.
• Experience using VHDL or Verilog.
• Strong organization, coordination,…