FPGA Design Engineer - Onsite

2026 Full Time - Raytheon FPGA Design Engineer I - Onsite

Join to apply for the 2026 Full Time - Raytheon FPGA Design Engineer I - Onsite role at Raytheon
.

Date Posted:

Country:
United States of America

Location:

AZ852: RMS AP Bldg M02 1151 East Hermans Road Building M02, Tucson, AZ, 85756 USA

Position Role Type:
Onsite

U.S. Citizen, U.S. Person, or Immigration Status Requirements:
Active and transferable U.S. government issued security clearance is required prior to start date. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance.

Security Clearance:
DoD Clearance:
Secret

At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world.

The Electrical Engineer will develop FPGA designs for all major vendors and device families including:
Xilinx, Intel, Microchip, and Lattice. Designs are implemented using VHDL and support the following type of applications: gigabit serial interfaces, Radio Frequency (RF) and Electro‑Optical (EO) Digital Signal Processing (DSP), control loops, data links, embedded processing, and processor interfaces. Configurable Logic Design Engineers work with circuit card designers and systems engineers to develop requirements, select parts, architect the device, perform code development, simulation, and place and route.

Designs are verified against requirements using both directed test and constrained random methodologies. Design support is expected from requirements definition through integration and test, and eventually production. Designs are documented and configuration managed throughout the entire design process.

• Bachelor’s degree in Electrical Engineering or related Science, Technology, Engineering and Mathematics (STEM) major.
• Experience with digital design and VHDL or Verilog coding.
• Familiarity with Xilinx, Altera or Microsemi/Microchip FPGAs.
• This position requires 12 months or less of relevant professional work experience (excluding internships).

• ABET is the preferred, although not required, accreditation standard. 3.0 cumulative GPA desired.
• Familiarity with the Linux environment and commands.
• Expertise of Xilinx, Intel, Microchip or Lattice devices and tool flows.
• Expertise in FPGA timing constraints and timing closure.
• Digital signal processing as applied to FPGA devices.

• Our values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value:
  Safety, Trust, Respect, Accountability, Collaboration, and Innovation.
• Relocation Eligibility.

The salary range for this role is 55,000 USD - 107,000 USD.

Hired applicants may be eligible for benefits, including but not limited to, medical, dental, vision, life insurance, short‑term disability, long‑term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays. Specific benefits are dependent upon the specific business unit as well as whether or not the position is covered by a collective‑bargaining agreement.

Hired applicants may be eligible for annual short‑term and/or long‑term incentive compensation programs depending on the level of the position and whether or not it is covered by a collective‑bargaining agreement. Payments under these annual programs are not guaranteed and are dependent upon a variety of factors including, but not limited to, individual performance, business unit performance, and/or the company’s performance.

This role is a U.S.

-based role. If the successful candidate resides in a U.S. territory, the appropriate pay structure and benefits will apply.

RTX anticipates the application window closing approximately 40 days from the date the notice was posted. However, factors such as candidate flow and…