Principal FPGA Design Engineer - Onsite Tucson, AZ

Overview

At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world.

The Effector Digital Products (EDP) department develops electronics for our weapon system products. We are responsible for the architecture, design, and documentation of deliverable FPGA embedded processing. We engage at the outset of the weapon system development and follow our designs through deployment. Our products are deployed all over the world, from the ground to exoatmospheric environments and into space.

Position
: Principal FPGA Design Engineer – you will develop FPGA designs for major vendors and device families including Xilinx, Altera, and Microsemi. Designs are implemented using VHDL for applications including gigabit serial interfaces, RF and EO DSP, controls, data links, embedded processing, and processor interfaces. This position is 100% onsite in Tucson, Arizona.

• Deliver production-quality FPGA releases from initial proof of concept to production
• Architect FPGA-based systems to determine parts, interfaces, and CONOPS
• Translate system-level requirements into FPGA requirements
• Design and code in VHDL for reliability and maintainability
• Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage
• Drive projects and execute program schedules on time and budget
• Create complete documentation including requirements, verification plans, and user’s guides
• Manage moderately sized projects or processes
• Viewed as subject-matter expert within discipline
• Able to operate with minimal oversight from manager
• Coaches, reviews, and delegates work to junior engineers
• Support internal and external technical reviews
• Support customer interactions and relations
• Make improvements to processes, systems or products to enhance overall performance

• Bachelor’s Degree in Electrical Engineering, Computer Engineering or Electrical Engineering Technology
• A minimum of eight (8) years of experience, including:
• FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
• Xilinx or Microsemi devices and flow tools
• Delivering FPGA/ASIC solutions to system level applications
• Hands-on experience with integration and debugging of FPGA/ASIC devices

• The ability to obtain and maintain a US security clearance prior to the start date. U.S. citizenship is required as only U.S. citizens are eligible for a security clearance.

• FPGA design experience in one or more of the following areas:
• Radar processing techniques
• Image processing techniques for visual and infrared sensors
• Embedded systems design using ARM, Microblaze, or Nios processors
• Gigabit serial interfaces and multi-gigabit transceivers (MGTs)

• Experience leading technical teams and programs

Our values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value:
Safety, Trust, Respect, Accountability, Collaboration, and Innovation.

• This position offers relocation

Salary range: 107,500 USD - 204,500 USD. Salary offers are a good faith estimate and depend on experience, location, and other factors. RTX provides benefits including medical, dental, vision, life insurance, disability coverage, 401(k) match, flexible spending accounts, paid time off, holidays, and more, as determined by the business unit and applicable law.

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status. RTX provides affirmative action in employment for qualified individuals with a disability and protected veterans in compliance with applicable laws.

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