ASIC Digital Verification Engineer

ASIC Digital Verification Engineer. We are looking for a highly skilled ASIC Digital Verification Engineer. In this role, you will drive verification strategy, develop advanced test environments, and ensure first‑silicon success for complex digital and mixed‑signal SoCs. If you enjoy solving challenging verification problems and collaborating across global design teams, this position will suit you well.

• Develop and execute comprehensive verification plans for block‑level, subsystem‑level, and full‑chip ASIC designs.

• Architect and implement UVM‑based verification environments, including test benches, sequences, scoreboards, and coverage models.

• Create and maintain constrained‑random and directed test suites to validate functionality, performance, and corner‑case behavior.

• Drive functional coverage closure and ensure verification completeness through metrics‑driven methodologies.

• Debug RTL, testbench, and simulation issues using industry‑standard tools and waveforms.

• Collaborate closely with RTL designers, architects, and cross‑functional teams to review specifications, identify verification gaps, and resolve design issues.

• Support gate‑level simulations, low‑power verification (UPF), and mixed‑signal verification as needed.

• Participate in code reviews, design reviews, and continuous improvement of verification methodologies and flows.

• BS in Electrical Engineering, Computer Engineering, or related field with 5–10 years of ASIC/SoC verification experience; MS with 3–7 years preferred.

• Strong expertise in System Verilog
  , UVM
  , and modern verification methodologies.

• Solid understanding of digital design fundamentals, RTL, and ASIC development flows.

• Hands‑on experience with simulation tools (e.g., VCS, Questa, Xcelium) and waveform debugging.

• Proficiency in scripting languages such as Python
  , Perl
  , TCL
  , or Shell for automation.

• Experience with functional coverage, assertions (SVA), and constrained‑random verification.

• Familiarity with protocols such as AMBA (AXI/AHB/APB), PCIe, DDR, or similar on‑chip interfaces.