FPGA Firmware Engineer

FPGA Firmware Engineer – Ulverston Hybrid or Remote (3 days on site per month, Tuesday to Thursday). Travel and accommodation fully expensed.

• FPGA Architecture & Real‑Time Signal Processing:
  • Develop FPGA designs for multi‑channel acoustic data acquisition, digital down conversion, filtering (FIR/IIR), FFT processing, beamforming algorithms, pulse compression and matched filtering.
  • Implement high‑speed streaming data pipelines.
  • Optimize fixed‑point arithmetic for deterministic real‑time performance.
  • Design low‑latency architectures for active sonar systems.
• High‑Speed Interface Development:
  • Implement and validate interfaces: high‑speed ADC/DAC, JESD
    204, LVDS, SERDES.
  • Develop memory interfaces (DDR3/DDR4) for buffering high‑bandwidth acoustic data.
  • Ensure deterministic timing and synchronization (e.g., PTP, trigger alignment).
• Hardware Integration & Subsea Considerations:
  • Collaborate with analogue and hardware engineers on front‑end acoustic transducer electronics, low‑noise acquisition chains, clocking strategies, and jitter management.
  • Consider power efficiency and thermal constraints in sealed subsea systems.
  • Contribute to design for reliability in harsh marine environments.
• Verification, Testing & Validation:
  • Develop simulation test benches for signal processing chains.
  • Perform bit‑accurate modelling (MATLAB/Python to RTL correlation).
  • Conduct hardware bring‑up and debug using integrated logic analyzers, oscilloscopes, spectrum analyzers.
  • Support acoustic tank testing and sea trials where required.
• Performance Optimisation:
  • Achieve timing closure for high‑speed DSP architectures.
  • Optimize FPGA resource usage (DSP slices, BRAM, LUTs). Minimise latency in signal paths.
  • Improve power efficiency for long‑duration subsea deployments.
• Documentation & Compliance:
  • Produce design documentation and verification reports.
  • Support compliance with relevant standards (EMC, CE, marine, defense).
  • Participate in design reviews and risk assessments (FMEA).

• Strong proficiency in VHDL and/or Verilog.
• Experience with Xilinx (AMD) or Intel FPGAs.
• Strong understanding of digital signal processing, fixed‑point arithmetic, FFT and filtering implementations, multi‑rate signal processing.
• Experience with high‑speed ADC/DAC interfacing.
• Knowledge of clock domain crossing and timing constraints.
• Familiarity with MATLAB or Python for DSP modelling.
• Degree in Electronic Engineering or related discipline.
• Postgraduate study in DSP, acoustics, or embedded systems (advantageous).

• Successful real‑time processing at required bandwidth.
• Timing closure at target clock frequencies.
• Low defect rate in sea trials.