FPGA Engineer R&D

Seeking motivated entry‑to‑senior level FPGA engineers to join the Applied Research Laboratory (ARL) at Penn State University. The role involves extensive knowledge in FPGA design and offers the opportunity to collaborate with researchers to develop next‑generation processing and analysis algorithms. ARL fosters training and mentorship to develop expertise in algorithm development.

Locations: onsite in State College, PA or Reston, VA, with potential hybrid options.

ARL is an authorized DoD Skill Bridge partner and welcomes all transitioning military members to apply.

• Design real‑time digital signal processing systems using FPGAs.
• Work on FPGA development and systems engineering.
• Define and coordinate interfaces within the systems.
• Develop and carry out hardware and firmware tests.
• Work on signal processing algorithm development and/or optimization.
• Analyze cost and risk factors involved in system development activities.
• Perform system verification and validation to ensure efficiency, reliability and compatibility.

This position will be filled at the professional, intermediate professional or advanced professional level, depending on education and work experience. Minimum requirement: a Bachelors’ degree in an Engineering or Science related discipline for the professional level.

• Intermediate professional level
• Mentor and/or train lower level employees and students.
• Lead specific FPGA tasks within the project scope.
• Contribute data/analysis/design for technical reports, documents, proposals, or presentations.
• Advanced professional level
• Manage FPGA projects of small or moderate size, ensuring quality, cost effectiveness and timeliness.
• Develop project status reports for appropriate distribution.
• Assist in concept development and participate in design analyses of engineering systems.
• Author or co‑author papers, proposals, presentations and reports on defined topics.
• Contribute to proposals, reports and presentations relating to FPGA efforts and maintain external research relationships.

• Experience designing and testing with FPGAs.
• Experience with VHDL and/or Verilog.
• Knowledge and exposure to prototyping, signal processing, FPGA, cellular, wireless, algorithms, communications and creative thinking.
• Programming/Scripting in MATLAB, Python, and/or C++ within a Linux environment.
• Ability to adapt technical strengths to new and adjacent areas of interest.
• Out‑of‑the‑box thinking to find creative solutions.
• Solid understanding of advanced math.

• Collaborate and learn with a team of researchers to develop cutting‑edge processing and analysis algorithms.
• Inquisitive mind and passion for developing best software and hardware solutions.

• Environment where you stretch yourself technically.
• Dynamic research environment for a variety of problems and tasks.
• Excellent work/life balance with generous time‑off policy.
• 75% off Penn State tuition for you and your family.

$76,700.00 – $

Candidate selected may be subject to a government security investigation. You must be a U.S. citizen to apply. Employment will require successful completion of a pre‑employment drug screen and background checks.

EEO IS THE LAW

Penn State is an equal opportunity employer and is committed to providing employment opportunities to all qualified applicants without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability or protected veteran status. If you are unable to use our online application process due to an impairment or disability, please contact 814‑865‑1473.

Employment with the University will require successful completion of background check(s) in accordance with University policies.