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Senior PLL Design Engineer — Mixed-Signal CMOS, On-Site NL

Job in 3515 AW, Utrecht, Utrecht, Netherlands
Listing for: Ethernovia
Full Time position
Listed on 2026-06-04
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering, Engineering Design & Technologists
Salary/Wage Range or Industry Benchmark: 100000 - 125000 EUR Yearly EUR 100000.00 125000.00 YEAR
Job Description & How to Apply Below
Ethernovia is seeking a Senior PLL Design Engineer to join our Mixed-Signal design team in Zeist, Netherlands. You will be involved in the architecture and implementation of advanced Phase-Locked Loops, collaborating closely with various technical teams.
This full-time role requires a Master's or PhD degree in Electrical Engineering and at least 8 years of experience in PLL design. The company offers a competitive package, excellent career development opportunities, and a supportive organizational culture.

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Position Requirements
10+ Years work experience
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