Senior PLL Design Engineer

Ethernovia is fundamentally changing how cars of the future are built by unifying in-vehicle networks into an end-to-end Ethernet system. Founded in 2018, we’re inventing the future of automobile’s communication! We are transforming automobiles’ communication network to enable the autonomous driving, electrical vehicle (EV) and software defined revolutions. Our breakthrough compute, communication, and software virtualization ushers in a new era of car connectivity and capabilities.

We bring together, accelerate, and unify the car’s cameras/sensors, compute, and outside world to enable new advanced driver assistance features and services.

Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.

With talented employees on 4 continents, we have filed > 50 patents to date.

Join Ethernovia’s team to make a lasting impact on the future of mobility. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive their design from concept to silicon to their next car.

Senior PLL Design Engineer
Summary

Ethernovia is a global 7+ year-old silicon solutions provider for  Automotive Ethernet  with a  HQ in Silicon Valley.

We are growing our  Mixed-Signal design  team, which is based in Zeist, The Netherlands.

We have a full-time opening for a Senior PLL designer who will  work on-site  in a team using  advanced CMOS processes

Driving the architecture and implementation of  advanced PLLs  (with challenging performance & efficiency specifications).

The work typically spans the planning & execution of a  full design cycle  from;

Specification, via study & design, test-chips and their evaluation, all the way to qualification and production.

All this not only in close collaboration with the Analog Front-End design and Layout teams, but also with the DSP, Digital, Firmware, and System teams, as well as Marketing & FAEs.

This obviously requires a  strong team-player mentality  of all involved, so expect professional colleagues with a focus on the end-goal, as well as the needs of team-members to reach it.

Furthermore, we are a growing and flexible start-up company which stimulates employees to broaden their experience & skills by learning new & exciting design challenges.

Skills & Qualification

A MSc or PhD degree in Electrical Engineering (EE)

At least 8 years of experience  in  PLL design  in  advanced CMOS nodes

Preferably also experience with  RTL, Verilog, C++ & Python

Experience in the domain of  Ethernet AFEs  is a plus

Team player with experience working in Mixed‑Signal IC design teams

Located in:
Utrecht, The Netherlands  or willing to locate to the Netherlands

What we offer

A full-time and indefinite contract

A competitive package (incl. stock option plan)

25 vacation days per year and annually one extra day with a maximum of 30 days

A fast-growing organization with excellent career and development opportunities

An open organizational culture where inputs from each are valued

An international environment with international colleagues and development sites on four continents

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