Director System Validation Engineer

Astera Labs (NASDAQ: ALAB) provides rack‑scale AI infrastructure through purpose‑built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor‑based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end‑to‑end scale‑up and scale‑out connectivity.

The company’s custom connectivity solutions business complements its standards‑based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.

Astera Labs is seeking an exceptional  Director System Validation  to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs’ fabric solutions perform at scale and deliver system‑level performance across the most demanding AI and ML workloads.

This role offers a unique opportunity to shape validation strategy for cutting‑edge connectivity silicon and gain deep insight into next‑generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world‑class validation organization tasked with validating all silicon, firmware, and system‑level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments.

Job Description

Seek a strong technical leader who has delivered multiple SoC products.

Lead and scale the system validation organization for Astera Labs' AI fabric portfolio, building a high‑performing team across multiple concurrent product programs.

Understand the performance and functionality requirements of our AI fabric switches to enable customers to develop data‑center systems using Astera Labs' connectivity products for AI and ML applications.

Own comprehensive validation strategies for AI fabric switch products. Drive execution through scalable automation platforms and data‑centric testing with automated reporting and specification compliance verification.

Collaborate cross‑functionally with Architecture, Hardware, Firmware, and Software teams to influence product requirements and ensure validation excellence.

Ensure timely bring‑up of new silicon and platforms, driving root‑cause analysis and cross‑functional debug of hardware, firmware, and system issues.

Deliver high confidence validation results that support product qualification, customer sampling, and mass production readiness.

Engage directly with key customers to understand their requirements and highlight the unique capabilities of Astera Labs' solutions.

The ideal candidate brings deep expertise in silicon/system validation, a strong architectural mindset, and a proven ability to scale organizations in fast‑moving, high‑performance computing environments.

Work closely with silicon design, architecture, Firmware, and software engineering teams to ensure cohesive validation strategies.

Drive a culture of technical excellence, accountability, and continuous improvement.

Manage resource planning, and vendor/partner relationships.

Basic Qualifications

Strong academic background in Electrical or Computer Engineering. Bachelor's required, Master's preferred.

≥15 years' experience supporting or developing complex SoC/silicon products for Server, Storage, Networking applications and high‑performance hardware companies.

≥5 years hands‑on experience with Silicon/System bring‑up, validation, and debug, including in customer systems.

≥2 years building high‑performance Engineering teams and validation methodologies.

Deep understanding of CPU, GPU, SoC, or AI/ML accelerator architectures, including memory subsystems, I/O, power management, and firmware interactions.

Expertise in validation methodologies: pre‑silicon simulation/emulation, post‑silicon bring‑up, system validation, stress testing, and performance characterization.

Strong background in debug…