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Senior ASIC Design Engineer at Celero
Job Description & How to Apply Below
Celero is actively seeking a skilled ASIC Design Engineer with substantial experience to design and develop high-performance ASICs. You'll utilize HDLs, conduct synthesis and analysis, and optimize designs for power and area. Collaborating with cross-functional teams, your contributions will be pivotal in refining cutting-edge technologies.
Key Responsibilities:
• Design digital circuits using HDL (Verilog/System Verilog)
• Conduct synthesis, timing analysis, and formal equivalence verification
• Optimize designs focusing on performance, power, and area
• Simulate and verify RTL designs for functionality
• Lead design reviews while guiding team members
Requirements:
• Bachelor’s or higher in a related field
• 3+ years of digital design and verification experience
• Proficiency with Verilog or System Verilog
• Strong understanding of digital design principles
• Familiarity with ASIC tools and flow methodologies
Bring your expertise in digital design to Celero and influence the future of AI and data infrastructure.
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Position Requirements
10+ Years
work experience
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