Senior Memory Layout Engineer
Job Description & How to Apply Below
Become a Senior Memory Layout Engineer with Infosys in Vancouver BC, where your expertise drives memory architecture innovation. Collaborate effectively on circuit design and layout optimization tasks.
This opportunity seeks seasoned professionals with a minimum of five years in Compiler/Custom Memory Layout design.
Your role will intersect with prior discussed technical knowledge, involving layout design from the ground up and performance optimization techniques while maintaining DRC integrity.
Key Responsibilities:
• Lead memory layout design and integration tasks
• Create libraries for memory leafcells from scratch
• Optimize layouts for enhanced performance
• Execute physical verification tasks including LVS checks
• Work collaboratively with circuit design teams
Requirements:
• At least 4 years of experience in Information Technology
• Bachelor’s degree or foreign equivalent in a related discipline
• Expertise in FinFET and layout technologies
• Familiarity with Cadence Virtuoso layout editor
• Committed to relocating or commuting to Vancouver
Bring your advanced layout design skills and passion for memory technologies to Infosys in this vital role.
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Position Requirements
10+ Years
work experience
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