Lead ASIC Design Engineer at Celero

Drive innovation as a Lead ASIC Design Engineer at Celero Communication Inc., specializing in next-gen optical technologies. Utilize your experience to shape the future of data centers.

In this pivotal role at Celero, you'll design and develop essential ASICs for optical transceivers. Expect to leverage HDL skills while focusing on optimization and verification processes. Your collaboration with diverse teams will ensure your designs meet challenging performance standards, reinforcing Celero's impact in the semiconductor sector.

Key Responsibilities:

• Design and implement digital circuits with HDL (Verilog/System Verilog)

• Conduct timing analysis and ensure formal verification

• Optimize ASIC designs for performance and power metrics

• Simulate RTL designs and verify functionality thoroughly

• Provide technical support and direction during design reviews

Requirements:

• Bachelor’s or higher degree in Engineering

• 3+ years in digital ASIC design and verification roles

• Expertise in Verilog and System Verilog

• Strong grasp of ASIC design methodologies

• Familiarity with low-power design techniques

Join Celero to advance your career, contributing to revolutionary technology in optical communications.
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