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Applications Engineering, Sr Engineer

Job in Vancouver, BC, Canada
Listing for: Synopsys
Full Time position
Listed on 2026-07-08
Job specializations:
  • Engineering
    Test Engineer, Electronics Engineer, Systems Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 CAD Yearly CAD 80000.00 100000.00 YEAR
Job Description & How to Apply Below

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You bring practical experience in semiconductor design with a strong foundation in power integrity, thermal integrity, or timing signoff. You have worked with tools like Red Hawk-SC, Prime Time, or Totem in production environments and understand what it takes to move a chip through signoff successfully.

You are comfortable working directly with customers, including highly technical experienced engineers. You listen well, ask the right questions, and know when to elevate to R&D versus solve the problem with existing capabilities. You can translate customer requirements into clear technical specifications that software teams can act on.

You bring a practical mindset to customer engagements. You understand that technical work must tie to business outcomes, and you balance depth with pragmatism. You are organized, self-directed, and able to manage multiple customer requests without losing track of priorities.

At Synopsys, you will support tier‑one accounts on problems that directly affect tape‑out schedules, working with a global team that values technical rigor and customer impact.

What You'll Be Doing
  • Support key accounts on power integrity, thermal integrity, and signal integrity signoff
  • Meet with customers multiple times a day to understand technical requirements, debug complex design issues, and deliver solutions that accelerate their tape‑out schedules
  • Translate customer needs into clear technical requirements for internal R&D teams, writing specs that bridge the gap between electrical engineering and software development
  • 3D‑IC power, multiphysics and thermal integrity signoff
  • Deploy and validate new workflows and integrated capabilities, including IR‑aware timing flows and thermal‑aware design methodologies, in live customer environment
  • Support both post‑sales deployments and pre‑sales engagements, helping customers adopt new tools and capabilities while ensuring existing workflows run smoothly
  • Build internal expertise on classic Synopsys tools and workflows, contributing to knowledge sharing and cross‑training efforts as the team integrates Ansys and Synopsys capabilities
  • Work with global engineering teams to align customer feedback with product roadmaps, ensuring that what you learn in the field shapes what gets built next
The Impact You Will Have
  • Drive adoption of Synopsys and Ansys signoff tools at tier‑one accounts, expanding our footprint in markets that define the future of AI and high‑performance computing
  • Help customers resolve complex power, thermal, timing, and reliability challenges that directly affect their ability to tape out on schedule
  • Influence the evolution of industry‑leading EDA products by feeding real customer use cases and technical gaps back to R&D teams
  • Strengthen customer relationships by acting as a trusted technical advisor who understands both the tools and the problems they are trying to solve
  • Improve internal capability through knowledge sharing, documentation, and cross‑training as the team builds expertise across the combined Synopsys and Ansys portfolio
What You'll Need
  • Bachelor's degree in Electrical Engineering with at least 2 years of experience, or Master's degree in Electrical Engineering with at least 1 year of experience
  • At least 1 year of hands‑on experience in semiconductor design with strong expertise in PDN/EMIR, static timing analysis, timing closure, thermal integrity, or ECO flows at block or SoC level
  • Hands‑on experience with tools such as Red Hawk‑SC, Red Hawk‑SC Electro Thermal, Totem, Totem‑SC, Prime Time, or Prime Closure
  • 3D‑IC architecture knowledge would be plus such as TSMC CoWoS‑L, interposer PDN design awareness
  • Strong understanding of signoff flows including power integrity, thermal integrity, timing analysis, and reliability
  • Ab…
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