Memory Layout Engineer Finfet Expertise

Position: Memory Layout Engineer with Finfet Expertise
Join a team pioneering in memory layout design as a Memory Layout Engineer specializing in Finfet technology.

Your role will involve hands-on layout design and verification for optimal performance in memory solutions.
As a seasoned designer with at least 5 years of experience, you will lead the creation of memory leafcell libraries and collaborate with circuit teams. Your deep understanding of memory architectures and physical verification processes such as DRC and LVS will ensure high-quality outputs. This position is critical in enhancing performance through efficient layout design.

Key Responsibilities:

• Work alongside circuit designers to achieve optimal layouts

• Develop memory leafcell layouts from scratch

• Enhance layout designs for improved performance

• Apply Finfet technology to layout challenges

• Conduct physical validation checks including DRC and LVS
Requirements:

• Minimum of 5 years' experience in memory layout design

• Knowledge of various memory architectures

• Strong Finfet layout design experience

• Expert in Cadence Virtuoso and Calibre verification

• Background in advanced nodes like 3nm, 5nm
Drive advancements in memory layout engineering with your expertise and passion for performance optimization.
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