RF Analog Layout Engineer at Technology Lead

Take charge as a Technology Lead in Analog Layout, focusing on RF/Analog IC Design. This full-time role emphasizes transistor-level layout development and optimization for high-performance circuits.

In this pivotal position, you will spearhead the design and verification of custom RF and analog layouts. Your expertise in FinFET technologies and deep sub-micron CMOS design is crucial for optimizing performance across advanced semiconductor platforms. Collaborate with RF designers and layout engineers ensuring precise and efficient layout delivery while leveraging tools like Cadence Virtuoso and Calibre.

Key Responsibilities:

• Design transistor-level layouts for RF/analog circuit blocks

• Perform layout verification using DRC, LVS, and ERC flows

• Optimize layouts for matching and parasitic reduction

• Collaborate with teams to deliver high-quality layouts

• Support FinFET-based designs in advanced nodes

Requirements:

• Strong experience in RF/Analog layout design

• Expertise in FinFET technologies (N5/N3/N2)

• Proficiency with Cadence Virtuoso Layout XL

• Knowledge of Calibre verification flows

• Understanding of deep sub-micron CMOS techniques

Excel in RF/Analog layout development and innovation while leading critical projects in cutting-edge semiconductor design.
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