Senior ASIC Physical Design Leader

Lead ASIC physical design for Cisco Silicon One hardware, specializing in fullchip floor planning, RTL-to-GDSII implementation, and timing closure.

As an ASIC Development Technical Leader, you will shape physical design methodology within Cisco’s Common Hardware Group. Your work spans hierarchical implementation, power integrity, physical verification, and performance, power, and die-size optimization. You will collaborate with system, package, RTL, DFT, implementation, EDA vendor, and tool-flow teams.

• Develop fullchip floor plans using architecture and foundry guidelines
• Perform partitioning, pin assignment, clock, and bump planning
• Execute RTL-to-GDSII implementation and physical verification
• Analyze flows and implement methodology enhancements
• Define signoff methods with foundry and standard-cell vendors

• Bachelor’s degree and eight-plus years’ physical design experience
• Master’s degree and six-plus years’ physical design experience
• PhD and three-plus years’ physical design experience
• RTL2
  
  GDSII and tapeout experience at 7nm, 5nm, or 3nm
• Experience with Innovus, Tempus, Prime Time, Red Hawk, Voltus, Calibre, or Pegasus

Apply fullchip physical design, timing, power integrity, and implementation expertise to Cisco’s advanced ASIC platforms.