Senior IC Verification Engineer – UVM​/SystemVerilog

A leading technology company in Vancouver is seeking a Design Verification Engineer for its Spectacles Team. You will work within a multi-disciplinary team focused on designing display Integrated Circuits for augmented reality. Candidates should have strong expertise in UVM and System Verilog, with over 10 years of experience in ASIC Design Verification. The role involves developing test benches, executing verification plans, and utilizing Siemens tools.

The company offers a competitive salary and a collaborative working environment, emphasizing diversity and inclusion.
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