Senior IC Verification Engineer – UVM​/SystemVerilog

A leading technology company based in Vancouver is seeking a Design Verification Engineer to join the Spectacles Team. This role involves developing UVM-based test benches and executing verification plans to enhance AR technologies. Ideal candidates should possess over 10 years of experience in ASIC Design Verification, with strong skills in System Verilog and digital functional simulation. The position offers a competitive salary range of $147,000 to $259,000 annually and requires collaboration with multi-disciplinary teams in a hybrid working environment.
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