Senior ESD​/Latch-Up Reliability Architect

Elevate memory reliability as a Senior ESD/Latch-Up Architect 'll define crucial ESD and latch-up strategies while collaborating on silicon validation and packaging in this advanced role.

This strategic position involves shaping the architecture for ESD protection across various domains including base die and advanced packaging. Your expertise will be essential in solving robust reliability challenges alongside multi-disciplinary teams. Drive the establishment of ESD standards and ensure successful correlation between design validation and actual field performance.

Key Responsibilities:

• Develop ESD architecture across memory systems and interconnects

• Create strategies for high-speed I/O and advanced packaging

• Establish ESD standards and component sign-off criteria

• Correlate design validation with field reliability metrics

• Partner with cross-functional teams to tackle ESD issues

Requirements:

• MS or PhD in Electrical Engineering or related field

• 10+ years in ESD/latch-up design and reliability roles

• Advanced knowledge of FinFET or GAA CMOS technologies

• Familiarity with 3D IC and die-to-die interfaces

• Demonstrated leadership in high-technology projects

Lead the way in ESD and latch-up reliability within Micron's innovative framework.
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