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FPGA Design Verification Engineer

Job in Wayne, Passaic County, New Jersey, 07474, USA
Listing for: Actalent
Full Time position
Listed on 2026-01-02
Job specializations:
  • Engineering
    Systems Engineer, Software Engineer
Salary/Wage Range or Industry Benchmark: 70.71 - 111 USD Hourly USD 70.71 111.00 HOUR
Job Description & How to Apply Below

FPGA Design Verification Engineer – DoD Secret Clearance

Job Description:

The role involves the design verification of VHDL developed for an FPGA, including DV planning, testbench infrastructure creation, testcase development, testing, debugging, and coverage closure. The code will be developed using System Verilog/Universal Verification Methodology (SV/UVM) following established styles and best practices. There may be opportunities to lead teams by developing schedules, tracking progress, allocating resources, and providing technical guidance.

Responsibilities
  • Create coverage and verification plan documents describing verification flows, constructs, and testbench usage.
  • Develop Work Breakdown Structure (WBS), Gantt charts, and other planning tools to show task breakdown, duration estimates, milestones, and task assignments.
  • Establish SV/UVM testbench infrastructure with environment, UVCs, monitors, predictors, checkers, and coverage collectors to verify the VHDL implementing FPGA functionality.
  • Develop SV/UVM testcases for configuring the testbench and generating stimulus to verify the FPGA functionality.
  • Prepare scripts and flows necessary for verification and simulation processes.
  • Track issues to ensure satisfactory resolution.
  • Maintain revision and release control of all design verification source code and documentation.
  • Generate code and functional coverage reports.
Essential Skills
  • Experience with FPGA design verification
  • Proficiency in System Verilog and Verilog
  • Knowledge of Universal Verification Methodology (UVM)
  • Active SECRET clearance
  • Familiarity with VHDL
  • Competence in using Xilinx and Mentor tool sets
Additional

Skills & Qualifications
  • Experience in developing SV/UVM testbench infrastructure
  • Ability to create scripts, constraints, and setup files related to the testbench
  • Capability to produce coverage and verification plan documents
  • Proficiency in generating code and functional coverage reports
Work Environment

This position requires 100% onsite work with potential hybrid flexibility. The organization operates on a 9/80 schedule, allowing employees to have every other Friday off. Candidates must hold an active SECRET clearance. Workplace is fully onsite in Wayne, NJ.

Pay & Benefits

The pay range for this position is $70.71 – $111.80/hr eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following:

  • Medical, dental & vision
  • Critical Illness, Accident, and Hospital
  • 401(k) Retirement Plan — Pre-tax and Roth post-tax contributions available
  • Life Insurance (Voluntary Life & AD&D for the employee and dependents)
  • Short and long-term disability
  • Health Spending Account (HSA)
  • Transportation benefits
  • Employee Assistance Program
  • Time Off/Leave (PTO, Vacation or Sick Leave)
Final date to receive applications

This position is anticipated to close on Dec 3, 2025.

Equal Opportunity Employer

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law. If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing due to a disability, please email for other accommodation options.

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